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A 320 MFLOPS CMOS floating-point processing unit for superscalar processors

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8 Author(s)
Ide, N. ; Toshiba Corp., Kawasaki, Japan ; Fukuhisa, H. ; Kondo, Y. ; Yoshida, T.
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A CMOS pipelined floating-point processing unit (FPU) for superscalar processors is described. It is fabricated using a 0.5 μm CMOS triple-metal-layer technology on a 61 mm2 die. The FPU has two execution modes to meet precise scientific computations and real-time applications. It can start two FPU operations in each cycle, and this achieves a peak performance of 160 MFLOPS double or single precision with an 80 MHz clock. Furthermore, the original computation mode, twin single-precision computation, double the peak performance and delivers 320 MFLOPS single precision. Its full bypass reduces the latency of operations, including load and store, and achieves an effective throughput even in nonvectorizable computations. An out-of-order completion is provided by using a new exception prediction method and a pipeline stall technique

Published in:

Solid-State Circuits, IEEE Journal of  (Volume:28 ,  Issue: 3 )

Date of Publication:

Mar 1993

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