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Synthesizing embedded speed-optimized architectures

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1 Author(s)
Gebotys, C.H. ; Dept. of Electr. & Comput. Eng., Waterloo Univ., Ont., Canada

A global optimization approach to high-level synthesis of speed-optimized embedded VLSI architectures is presented. Two mathematical integer programming (IP) models are presented. The first simultaneously selects types of functional units, performs scheduling tasks, and allocates hardware. The second additionally minimizes latency and optimally selects a clock period simultaneously with scheduling and allocation. By exploiting the problem structure, using polyhedral theory, the size of the search space of both IP models is decreased, thus improving the IP solution efficiency. This approach breaks new ground by simultaneously scheduling and allocating with complex and asynchronous interface constraints, to minimize both the average execution time and the area, automatically minimizing latency by optimally selecting the clock period and types of functional units (including chained operations), and synthesizing globally optimal architectures of embedded VLSI chips in practical CPU execution times

Published in:

Solid-State Circuits, IEEE Journal of  (Volume:28 ,  Issue: 3 )

Date of Publication:

Mar 1993

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