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Sizing of cell-level analog circuits using constrained optimization techniques

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3 Author(s)
Maulik, P.C. ; Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA ; Carley, L.R. ; Allstot, D.J.

A CAD tool that accurately sizes analog circuits in short-channel CMOS processes using SPICE-quality device models and constrained optimization techniques is presented. All knowledge about device behavior is embedded within an encapsulated device evaluator which simplifies the description of the analog circuit that must be provided by an expert designer, and makes that description independent of the specific device type and technology. The use of constrained optimization allows the KCL and KVL constraints that determine the DC operating point of a circuit to be formulated and solved for simultaneously with the performance constraints. In addition, the constrained optimization formulation of the analog design problem makes it easy for the user to study trade-offs in the circuit design space by varying the performance constraints. Simulation results demonstrate the tool's ability to accurately synthesize high-performance two-stage CMOS operational amplifiers in 2 μm and 1.2 μm CMOS processes

Published in:

Solid-State Circuits, IEEE Journal of  (Volume:28 ,  Issue: 3 )

Date of Publication:

Mar 1993

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