By Topic

An image processing IC for backprojection and spatial histogramming in a pipelined array

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

3 Author(s)
I. Agi ; California Univ., Davis, CA, USA ; P. J. Hurst ; K. W. Current

The first VLSI digital signal processor that performs both high-precision image backprojection and spatial histogram calculations at raster-scan rates as high as 30 MHz is described. Realized in 1 μm CMOS technology, this 13.3 mm×13.3 mm chip is designed to handle images as large as 1024×1024 12 b pixels. Loadable coefficients and a unified architecture allow this IC to be used with a variety of computed-tomography scanners for image reconstructions, including fan- and parallel-beam reconstruction. This chip also computes the forward Radon transform, which is a spatial histogram, permitting it to be used for iterative reconstruction algorithms. The bit lengths in the fixed-point architecture assure 12 b reconstruction accuracy

Published in:

IEEE Journal of Solid-State Circuits  (Volume:28 ,  Issue: 3 )