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A 120 K-gate usable CMOS sea of gates packing 1.3 M transistors

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5 Author(s)
Suehiro, Y. ; Fujitsu Ltd., Kawasaki, Japan ; Miura, D. ; Naitoh, M. ; Tsutsumi, S.
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A CMOS sea of gates with 160 K basic cells for random logic and memories is reported. Because of the unique architecture, the LSI offers flexible configuration of RAMs, ROMs, and PLAs (programmable logic arrays) with high density and suitable routing areas for random logic circuits, and results in the utilization of 120 K basic cells. It is fabricated with CMOS 1.0-μm triple-metal-layer process technology

Published in:

Custom Integrated Circuits Conference, 1988., Proceedings of the IEEE 1988

Date of Conference:

16-19 May 1988