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A flexible approach to test generation for scan design circuits

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3 Author(s)
Bayliss, J.S. ; GenRad Ltd., Fareham, UK ; Guyler, I.A. ; Wallace, M.R.

A solution to testing VLSI is the use of a Design-for-test structured technique which improves the observability and controllability of the circuit. One such technique, known as SCAN, requires that registers can be configured so that they can be serially loaded and read directly from the device's pins. Every register is now controllable and observable allowing test generation software to achieve maximum fault coverage with a few test vectors. Scan designs typically have a 10% to 15% silicon overhead and require three additional device pins. However, with an appropriate test generation tool, test preparation time for scan designs can be reduced from weeks to hours

Published in:

Design for Testability, IEE Colloquium on

Date of Conference:

3 Mar 1988