A description is given of an integrated empirical modeling methodology which has been successfully applied in modeling the ASPECT process (Advanced Single Poly Emitter Coupled Technology) to ensure manufacturable circuit designs. The accuracy which has been achieved with this degree of modeling has contributed significantly to realizing `right the first time' designs on a number of standard cell VLSI ECL (emitter-coupled logic) designs. A comprehensive test chip was used to construct a database composed of both single-point and multipoint measurements along with capacitance voltage behavior,
Published in:
Custom Integrated Circuits Conference, 1988., Proceedings of the IEEE 1988
Date of Conference: 16-19 May 1988