A CMOS 10 bit accuracy and 5 mu S speed AD converter

A novel architecture consisting of successive-approximation A-D (analog-to-digital) conversion has been used to realize a low-cost 10-bit-accuracy A-D converter composed of a small number of components without self-calibration or trimming. A high-speed auto-zeroed comparator has achieved 5- mu s A-D conversion. The chip is fabricated by a conventional 2.5- mu m CMOS process with a die size of 8.1 mm/sup 2/.<
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