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A CMOS 10 bit accuracy and 5 μS speed AD converter

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4 Author(s)
Iida, T. ; Toshiba Semicond. Syst. Eng. Center, Kawasaki, Japan ; Gotoh, J. ; Nishizuka, A. ; Hara, H.

A novel architecture consisting of successive-approximation A-D (analog-to-digital) conversion has been used to realize a low-cost 10-bit-accuracy A-D converter composed of a small number of components without self-calibration or trimming. A high-speed auto-zeroed comparator has achieved 5-μs A-D conversion. The chip is fabricated by a conventional 2.5-μm CMOS process with a die size of 8.1 mm2

Published in:

Custom Integrated Circuits Conference, 1988., Proceedings of the IEEE 1988

Date of Conference:

16-19 May 1988