The architectures and design of a 20-MHz real-time DSP

A set of four real-time 20-MHz digital signal processor (DSP) chips have been designed, fabricated, and tested. The chips include a 64-tap programmable FIR (finite-impulse response) filter, a 1024-tap binary filter and template matcher, a 64-tap rank-value filter, and an eight-line 512-pixel video-line delay. All of the circuits were implemented in a 1.5- mu m CMOS process and are fully functional with a 20-MHz clock rate.<
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