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A 50 MIPS multiprocessor chip for image processing

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3 Author(s)
Denayer, T. ; Lab. de Microelectron., Univ. Catholique de Louvain, Belgium ; Vanzieleghem, E. ; Jespers, P.

A 50-MIPS (million-instruction-per-second) 90000-transistor CMOS multiprocessor chip is described. It has been designed as a building block for orthogonal transforms of TV images in a bandwidth-reduction system. 64 processing elements (serial parallel multipliers) are assembled in a systolic-like architecture. Because of its modularity, the chip can be used for matrix products of arbitrary size

Published in:

Custom Integrated Circuits Conference, 1988., Proceedings of the IEEE 1988

Date of Conference:

16-19 May 1988