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An ASIC controller for the TMS 320, 2-generation digital signal processor

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4 Author(s)
Creanza, G. ; Tecnopolis Casta, Valenzano, Italy ; Ventrella, O. ; Colangeli, G. ; Subiaco, E.

The authors deal with an ASIC that integrates all the glue logic that allows one or more DSPs, organized in a multiprocessor, linear array system, to communicate with their memories, with a host processor and among themselves. This circuit has been developed as a gate array in the ALCATEL FACE research center with the collaboration of TECNOPOLIS CSATA

Published in:

Euro ASIC '90

Date of Conference:

29 May-1 Jun 1990

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