Cart (Loading....) | Create Account
Close category search window
 

Dual port static RAM testing

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

1 Author(s)
Raposa, M.J. ; Sun Microsyst. Inc., Mountain View, CA, USA

The basics are presented of a test methodology used for dual-port static RAMs (random-access memories). The fundamental problem in testing dual-port static RAMs is how to address the entire array from both sides individually. Any memory tester with dual pattern generators and dual timing systems would suffice, but most existing memory testers were designed and built before dual-port static RAMs were introduced, and offer no such solution. The following three methods have been proposed, and the advantages and disadvantages of each one explored. They are: same address, both ports; complement address; and separation of ports

Published in:

Test Conference, 1988. Proceedings. New Frontiers in Testing, International

Date of Conference:

12-14 Sep 1988

Need Help?


IEEE Advancing Technology for Humanity About IEEE Xplore | Contact | Help | Terms of Use | Nondiscrimination Policy | Site Map | Privacy & Opting Out of Cookies

A not-for-profit organization, IEEE is the world's largest professional association for the advancement of technology.
© Copyright 2014 IEEE - All rights reserved. Use of this web site signifies your agreement to the terms and conditions.