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Design for testability of a 32-bit microprocessor-the TX1

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3 Author(s)
Nozuyama, Y. ; Toshiba Corp., Kawasaki, Japan ; Nishimura, A. ; Iwamura, J.

Testable designs of the TX1, a 32-bit microprocessor based on the TRON architecture, are described. Clear testing strategies were developed, resulting in three testable design approaches implemented in an optimized form. Logic function test is composed of scan test and self test. Their efficiency is highly enhanced by the use of the bus structure or microinstruction set of the TX1. Fault coverage of over 90% is achieved by them with short testing time (several seconds) and small increase of chip area (4.2%). Design verification is done with scan test and macroblock test. The latter can directly test important manually designed hardware blocks independent of the complicated decode and control logic. The area increase is only 0.4%. It can give useful information for their refinement in the early phase of development

Published in:

Test Conference, 1988. Proceedings. New Frontiers in Testing, International

Date of Conference:

12-14 Sep 1988