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A compile-time scheduling heuristic for interconnection-constrained heterogeneous processor architectures

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2 Author(s)
Sih, G.C. ; Qualcomm Inc., San Diego, CA, USA ; Lee, E.A.

The authors present a compile-time scheduling heuristic called dynamic level scheduling, which accounts for interprocessor communication overhead when mapping precedence-constrained, communicating tasks onto heterogeneous processor architectures with limited or possibly irregular interconnection structures. This technique uses dynamically-changing priorities to match tasks with processors at each step, and schedules over both spatial and temporal dimensions to eliminate shared resource contention. This method is fast, flexible, widely targetable, and displays promising performance

Published in:

Parallel and Distributed Systems, IEEE Transactions on  (Volume:4 ,  Issue: 2 )

Date of Publication:

Feb 1993

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