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A study of failures identified during board level environmental stress testing

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2 Author(s)
T. P. Parker ; AT&T Little Rock, AR, USA ; C. W. Webb

AT&T has investigated and implemented environmental stress testing (EST) in the production of a variety of circuit board designs as a means of reducing the incidence of early life failures. EST techniques include thermal cycling (TC), random vibration, etc. These techniques have proven more effective than traditional burn-in techniques. In addition, studies have revealed that functional monitoring during thermal stressing of circuit cards more than doubles the effectiveness of EST. Outgoing quality audits and customer first month failure rates have improved by factors of two to four since the implementation of EST

Published in:

IEEE Transactions on Components, Hybrids, and Manufacturing Technology  (Volume:15 ,  Issue: 6 )