By Topic

A cyclic charge-balancing A/D converter with capacitor mismatch error compensation

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

3 Author(s)
Tsukamoto, K. ; Dept. of Electr. & Electron. Eng., Ibaraki Univ., Hitachi, Japan ; Miyata, T. ; Takagi, T.

An algorithm is proposed for improving the speed of a charge-balancing analog-to-digital converter implemented by a switched-capacitor technique. The number of charge transfer operations required for a conversion is reduced. For example, the conversion rate in 16-b conversion is improved more than 128 times as compared to a conventional charge-balancing analog-to-digital converter. A compensation algorithm for the capacitor mismatch error is also proposed. The results of prototype experiments indicate that the maximum integral nonlinearity error is reduced to less than 0.04 LSB in 6-b conversion

Published in:

Instrumentation and Measurement, IEEE Transactions on  (Volume:42 ,  Issue: 1 )