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Parallel switch-level simulation for VLSI

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3 Author(s)
R. B. Mueller-Thuns ; Center for Reliable & High Performance Comput., Illinois Univ., Urbana, IL, USA ; D. G. Saab ; J. A. Abraham

Switch-level simulation is widely used in the design verification process of Very Large Scale Integrated (VLSI) MOS circuits. In this paper, the authors present methods for accelerating switch-level simulation by mapping it onto general purpose parallel computers. Their target machines are medium-grain multiprocessors (shared memory or message passing machines) and they only consider model parallel computation, where the model of the design to be simulated is partitioned among processors. Efficient strategies are introduced for circuit partitioning as well as the corresponding simulation algorithms. In the authors' approach, they try to minimize the total number of synchronizations between processors, as well as ensure portability and scalability. A preprocessor and simulator were implemented and good performance was obtained for a set of benchmarks. The problem of tight coupling between processors that evaluate a strongly connected component in the circuit in a distributed fashion is highlighted

Published in:

Design Automation. EDAC., Proceedings of the European Conference on

Date of Conference:

25-28 Feb 1991