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An integrated layout system for sea-of-gates module generation

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3 Author(s)
P. Duchene ; Electron. Labs., Federal Inst. of Technol., Lausanne, Switzerland ; M. Declercq ; S. M. Kang

Presents a sea-of-gates layout system able to design medium-size logic circuits in a true channelless fashion. The methodology relies on flexible leaf cell generation, systematic cell terminal abutment, a global routine scheme using integer linear programming methods, and a step-wise compaction-rerouting refinement. Modules up to several hundred transistors have been laid out compactly with more than 80% transistor utilization with two layers of metal. With top-down hierarchy, those modules can be used as macrocells

Published in:

Design Automation. EDAC., Proceedings of the European Conference on

Date of Conference:

25-28 Feb 1991