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A graph-based silicon compiler for VLSI systems

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1 Author(s)
Allerton, D.J. ; Dept. of Electron. & Comput. Sci., Southampton Univ., UK

A silicon compiler has been developed which can translate from SCHOLAR high-level specifications to a netlist suitable for layout and fabrication. A number of different designs have been implemented in order to make comparisons between this approach to silicon compilation and more traditional routes to silicon. In addition to speed/area comparisons, this approach also provides significant improvements in the amount of effort in specification and design, compilation turnaround times are typically reduced to less than one hour and the possibility of manual transcription errors is effectively eliminated

Published in:

Silicon Compilation, IEE Colloquium on

Date of Conference:

24 May 1989

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