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Application-specific architecture for fast transforms based on the successive doubling method

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2 Author(s)
E. L. Zapaga ; Dept. Arquitectura de Computadores, Malaga, Spain ; F. Arguello

The successive doubling method is an efficient procedure for the design of fast algorithms for orthogonal transforms of length N=rn, where the radix r is a power of 2. A partitioned systolic architecture is presented for the two standard radix successive doubling algorithms: decimation in time (DIT) and decimation in frequency (DIF). The index space of the data is projected onto the index space associated with a column of processors, interconnected using a perfect unshuffle (DIT) or shuffle (DIF) interconnection network, defined by permutations of the order log2 r. The result is a partitioned systolic array with Q processors (Q=ri, 0⩽i<n), which extracts the maximum spatial and temporal parallelism achieved by the successive doubling algorithm and can be integrated in VLSI and WSI technologies

Published in:

IEEE Transactions on Signal Processing  (Volume:41 ,  Issue: 3 )