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Serial-parallel FFT array processor

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2 Author(s)
J. You ; Sch. of Electron. Eng., Hongik Univ., Seoul, South Korea ; S. S. Wong

An array architecture for computing a fast Fourier transform (FFT) with a flexible number of identical processing elements is presented. The architecture is based on the symmetry of a constant geometry FFT. It allows an easy tradeoff between the hardware complexity and the computation time. A method for constructing a high-radix FFT with simple lower-radix hardware based on successive decompositions and premultiplications has been developed. It shows that a high-radix, lengthy FFT can be efficiently implemented with simple hardware. To verify the architecture, an experimental radix-2 processing element chip has been designed and the results are discussed

Published in:

IEEE Transactions on Signal Processing  (Volume:41 ,  Issue: 3 )