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Logic transformations for synchronous logic synthesis

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2 Author(s)
De Micheli, G. ; Comput. Syst. Lab., Stanford Univ., CA, USA ; Yip, R.

An approach to logic synthesis of digital synchronous sequential circuits is presented. Algorithms are described for minimizing the area of synchronous combinational and/or sequential circuits under cycle time constraints and for minimizing the cycle time under area constraints. It is shown how to optimize concurrently the circuit equations and the register position by a set of algorithms based on logic transformations. An implementation of the algorithms in the program Minerva is described, and experimental results are reported

Published in:

System Sciences, 1990., Proceedings of the Twenty-Third Annual Hawaii International Conference on  (Volume:i )

Date of Conference:

2-5 Jan 1990