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A new method for hierarchical compaction [VLSI]

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2 Author(s)
Rulling, W. ; Fachhochschule Furtwangen, FB Ingenieur-Inf., Germany ; Schilz, T.

A framework for the compaction of hierarchically specified layout sketches is proposed. The main advantage of the method is that it maintains the layout hierarchy. Thus, the produced output has the same efficient representation as the input and further efficient processing of the layout becomes possible

Published in:

Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on  (Volume:12 ,  Issue: 2 )