By Topic

The benefits of flexibility in lookup table-based FPGAs

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)
Hill, D. ; AT&T Bell Labs., Murray Hill, NJ, USA ; Nam-Sung Woo

FPGAs (field programmable gate arrays) need not be limited to a single fixed-size truth table in each block. The authors discuss the utility of allowing each block's single large table (e.g. one 5-input, 32-b table) to be reconfigured into smaller tables (e.g. eight 4-b tables). Results describing the efficiency of packing some standard benchmark circuits into various configurations are presented and the cost/benefits discussed. It is shown that a logic block containing four lookup tables, each of which is 8-b RAM, is the best choice if only the area efficiency is considered. It is also shown that if circuit speed is considered, a logic block containing two lookup tables, each of which contains 16 b of RAM, is the best choice

Published in:

Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on  (Volume:12 ,  Issue: 2 )