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An exact zero-skew clock routing algorithm

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1 Author(s)
Ren-Song Tsay ; IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA

An exact zero-skew clock routing algorithm using the Elmore delay model is presented. The results have been verified with accurate waveform simulation. The authors first review a linear time delay computation method. A recursive bottom-up algorithm is then proposed for interconnecting two zero-skewed subtrees to a new tree with zero skew. The algorithm can be applied to single-staged clock trees, multistaged clock trees, and multi-chip system clock trees. The approach is ideal for hierarchical methods of constructing large systems. All subsystems can be constructed in parallel and independently, then interconnected with exact zero skew. Extensions to the routing of optimum nonzero-skew clock trees (for cycle stealing) and multiphased clock trees are also discussed

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Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on  (Volume:12 ,  Issue: 2 )