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Critical path selection for performance optimization

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3 Author(s)
H. -C. Chen ; Dept. of Comput. Sci., Minnesota Univ., Minneapolis, MN, USA ; D. H. -C. Du ; L. -R. Liu

The problem of selecting a set of paths to optimize the performance of a combinational circuit is studied, assuming that gate resizing and buffer insertion are the two possible optimizing techniques for reducing the delay of a circuit. The objective of the path selection problem is to select as small as possible a set of paths to ease the optimization processing to guarantee that the delay of the circuit is no longer than a given threshold τ if the delays of all the selected paths are no longer than τ. It is shown that the path selection is different from path sensitization. An input vector-oriented path selection algorithm is proposed. Because it may be infeasible for complex circuits with many primary inputs, a path-oriented algorithm is also developed and implemented. Experimental results on ISCAS85 benchmark circuits show a potentially big improvement for the optimization process

Published in:

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  (Volume:12 ,  Issue: 2 )