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Reducing iteration time when result digit is zero for radix 2 SRT division and square root with redundant remainders

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2 Author(s)
Montuschi, P. ; Dipartimento di Autom. e Inf., Politecnico di Torino, Italy ; Ciminiera, L.

A new architecture is presented for shared radix 2 division and square root whose main characteristic is the ability to avoid any addition/subtraction, when the digit 0 has been selected. The solution presented uses a redundant representation of the partial remainder, while keeping the advantages of classical solutions. It is shown how the next digit of the result can be selected even when the remainder is not updated, and the subsequent tradeoff is presented. The proposed architecture is also extended in order to consider other implementations

Published in:

Computers, IEEE Transactions on  (Volume:42 ,  Issue: 2 )

Date of Publication:

Feb 1993

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