By Topic

Improved systolic allpass digital filters for very high-speed applications

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $33
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

1 Author(s)
H. K. Kwan ; Dept. of Electr. Eng., Windsor Univ., Ont., Canada

An improved systolic realisation of an arbitrary-order allpass digital filter for delayed N-path digital filtering is presented. Using this method, the sampling rate at the input and output of a delayed N-path digital filter can be reduced to (Tm+2Ta)/(N(N-1)) (where N>or=2, and Tm and Ta, respectively, represent the times for 2-input real multiplication and 2-input real addition), which is attractive for very high-speed applications.

Published in:

Electronics Letters  (Volume:28 ,  Issue: 22 )