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Designing circuits with partial scan

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4 Author(s)
Agrawal, V.D. ; AT&T Bell Labs., Murray Hill, NJ, USA ; Kwang-Ting Cheng ; Johnson, D.D. ; Sheng Lin, T.

In this scan design methodology, only selected faults are targeted for detection. These faults are those not detected by the designer's functional vectors. The test generator decides exactly which flip-flops should be scanned using one of two methods. In the first method, all possible tests are generated for each target fault, and the set of tests requiring the fewest flip-flops is selected. In the second method, only one test is generated for each fault, and the use of flip-flops is avoided as much as possible during test generation. Examples of actual VLSI circuits show a savings of at least a 40% in full-scan overhead.<>

Published in:

Design & Test of Computers, IEEE  (Volume:5 ,  Issue: 2 )