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A coupled study by floating-gate and charge-pumping techniques of hot carrier-induced defects in submicrometer LDD n-MOSFET's

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5 Author(s)
Vuillaume, D. ; Inst. d''Electron. et de Microelectron. du Nord, CNRS, Lille, France ; Marchetaux, J.-C. ; Lippens, P.-E. ; Bravaix, A.
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The creation of defects by hot-carrier effect in submicrometer (0.85-μm) LDD n-MOSFETs is analyzed by the floating-gate and the charge-pumping techniques. It is emphasized that the floating-gate technique is an attractive tool for characterizing the oxide traps located in the drain-gate overlap region, near the oxide spacer of the LDD structures. This work gives new insight into the creation of acceptorlike oxide traps which are electrically active only after electron injection phases. These defects are generated in the whole stress gate bias range (from Vd/8 to Vd) by hot-hole and/or hot-electron injections, and their generation rates (10-9 and 10-2 for electron and hole injections, respectively) are one decade greater than for the interface state generation. Two-dimensional simulations show that they are mainly responsible for the Id-Vg degradation of the LDD MOSFETs, and that the trap concentrations deduced from charge-pumping experiments are consistent with the I d-Vg degradation

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Electron Devices, IEEE Transactions on  (Volume:40 ,  Issue: 4 )