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An analytical back-gate bias effect model for ultrathin SOI CMOS devices

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2 Author(s)
Jai-Hoon Sim ; Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan ; Kuo, J.B.

An analytical back-gate bias effect model for ultrathin SOI CMOS devices is presented. As verified by PISCES results, the analytical SOI CMOS back-gate bias effect model provides a much better accuracy in the integral potential distribution and the threshold voltage as the back-gate bias is changed

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Electron Devices, IEEE Transactions on  (Volume:40 ,  Issue: 4 )