We are currently experiencing intermittent issues impacting performance. We apologize for the inconvenience.
By Topic

Variability reduction in CMOS operational amplifiers through layout modification

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $31
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)
Bhattacharyya, A.B. ; Centre for Appl. Res. in Electron., Indian Inst. of Technol., New Delhi, India ; Aggarwal, S.

A variability analysis for a CMOS operational amplifier has been performed by a technique based on the sensitivity information of the performance parameters with respect to the process-component parameters. The variability of the offset voltage has been computed with respect to the threshold voltage. Three-level statistical data of the threshold voltage have been obtained for use in the variability computations. Based on the sensitivity analysis, an improved layout has been prepared to reduce variability by matching the components having opposite sensitivities, some of which are seemingly unrelated. The CMOS operational amplifier has been fabricated with both the basic and proposed layouts in p-well, Si-gate technology with a 5 mu m design rule. Experimentally observed statistical data for the offset voltage show a reduction in variability with the proposed layout as predicted by theoretical computations.

Published in:

Circuits, Devices and Systems, IEE Proceedings G  (Volume:136 ,  Issue: 2 )