By Topic

Design of a language for IC mask verification and net extraction

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $33
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)
A. D. Brown ; Dept. of Electron., Southampton Univ., UK ; P. R. Thomas

Describes the design of a language (the Mask Verification Language, or MVL) to interface with a programmable mask analysis system to check technology rules and extract netlists in a low-cost computing environment. The system operates in batch mode, i.e. mask designs are presented to the system, which checks them and reports errors. If there are problems, the mask designer can re-enter the mask editor to correct them. Running on a single-user workstation, the development loop has been found to be very fast. Legal devices and the technology description are presented to the system in MVL. Each device description contains a descriptive part which controls how a device is recognised, and a procedural part which controls how it is verified and processed once it has been recognised.

Published in:

IEE Proceedings G - Circuits, Devices and Systems  (Volume:136 ,  Issue: 2 )