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Design of a language for IC mask verification and net extraction

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2 Author(s)
Brown, A.D. ; Dept. of Electron., Southampton Univ., UK ; Thomas, P.R.

Describes the design of a language (the Mask Verification Language, or MVL) to interface with a programmable mask analysis system to check technology rules and extract netlists in a low-cost computing environment. The system operates in batch mode, i.e. mask designs are presented to the system, which checks them and reports errors. If there are problems, the mask designer can re-enter the mask editor to correct them. Running on a single-user workstation, the development loop has been found to be very fast. Legal devices and the technology description are presented to the system in MVL. Each device description contains a descriptive part which controls how a device is recognised, and a procedural part which controls how it is verified and processed once it has been recognised.

Published in:

Circuits, Devices and Systems, IEE Proceedings G  (Volume:136 ,  Issue: 2 )