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Exploiting bit-level parallelism in Boolean matrix operations for graph analysis

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3 Author(s)
Jackson, D.J. ; Dept. of Electr. Eng., Alabama Univ., Tuscaloosa, AL, USA ; Whiteside, D.M. ; Wurtz, L.T.

A number of important characteristics for a graph, which may represent a set of parallel application tasks or a parallel computer architecture, can be extracted by analyzing the Boolean matrix corresponding to the graph. The characteristic of concern is the determination of minimum path lengths for various classes of regularly structured graphs. All the example graphs vary in terms of connectivity and sparsity and provide a suitable testbed for the analysis of the various algorithms used in determining powers of the Boolean matrices. Improvements for these algorithms are introduced which exploit the Boolean nature of the matrices and the inherent bit-level parallelism available in any N-bit computer system. An algorithm is introduced which exploits this bit-level parallelism and a number of graphs were analyzed utilizing a high-performance IBM RS/6000 workstation to demonstrate the merits of the algorithm

Published in:

Southeastcon '92, Proceedings., IEEE

Date of Conference:

12-15 Apr 1992