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A hybrid architecture for a high performance and physical small low-level image processing system

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2 Author(s)
van Inge, A. ; Dept. of Comput. Sci., Amsterdam Univ., Netherlands ; Hertzberger, L.O.

Deals with the hardware implementation of a low-level image processing unit for mobile autonomous systems. High processing performance and a small physical size of the sensor and processing unit are two important factors. The image processing unit described here combines between high system performance and flexibility. The emphasis for this design lies on two aspects, i.e. adapted processors, in this case SIMD processor-arrays, and guided data reduction by means of finding partial images

Published in:

Pattern Recognition, 1992. Vol. IV. Conference D: Architectures for Vision and Pattern Recognition, Proceedings., 11th IAPR International Conference on

Date of Conference:

30 Aug-3 Sep 1992

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