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High performance BiCMOS technology design for sub-10 ns 4 Mbit BiCMOS SRAM with 3.3 V operation

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7 Author(s)
Maeda, T. ; Toshiba Corp., Kawasaki, Japan ; Gojohbori, H. ; Inoue, K. ; Ishimaru, K.
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A high-performance 0.5- mu m BiCMOS technology for 4-Mb BiCMOS SRAM for low-voltage operation is discussed. 1.5* performance improvement and low power relative to 0.8- mu m BiCMOS technology are achieved with reduced operation of 3.3 V. In particular, although power-supply voltage is reduced, none of device performance is so severe as to constrain the feasibility of a 0.5- mu m and below BiCMOS technology even for a high-density 4-Mb SRAM. A 16-b 4-Mb BiCMOS SRAM was fabricated to prove the developed 0.5- mu m BiCMOS technology combined with a quadruple poly Si and double Al process. The cell size is 3.5 mu m*5.7 mu m, and the chip size is 8.7mm*18.8 mm. Parametric testing of the 4-Mb BiCMOS SRAM confirmed the expected 9-ns access time at 3.3-V operation. Moreover, the total power dissipation can be managed below 500 mW, which is available for plastic packaging.<>

Published in:

VLSI Technology, 1992. Digest of Technical Papers. 1992 Symposium on

Date of Conference:

2-4 June 1992