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Key issues in the design of a fault-tolerant core avionics computer based on the mesh architecture

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3 Author(s)
Nordsieck, A.W. ; Boeing High Technol. Center, Seattle, WA, USA ; Yost, W.M. ; Young, C.A.

Greater integration of avionics and flight control electronics with the need for higher reliability while maintaining or improving safety and availability and the need for reduced line maintenance costs are key drivers for the examination of a fault tolerant core computer architecture. The authors' approach is to develop a computer using commercially available microprocessors and memory with an ASIC performing the fault management. They use a tightly synchronous mesh architecture with distributed dynamic fault detection, isolation and reconfiguration. They examine key impediments to the achievements of fault tolerance for the mesh architecture

Published in:

Defect and Fault Tolerance on VLSI Systems, 1991. Proceedings., 1991 International Workshop on

Date of Conference:

18-20 Nov 1991