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Improved yield models for fault-tolerant random-access memory chips

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1 Author(s)
Stapper, C.H. ; IBM Gen. Technol. Div., Essex Junction, VT, USA

Several improvements in the method of yield modeling for memory chips with redundancy are described. First, a direct method of translating defect-monitor data to memory-chip faults eliminates the need for yield-model formulas, making possible accurate modeling of the faults that can be fixed with redundant circuits or other fault-tolerance techniques. This results in loosely coupled distributions instead of the multivariate distributions used until now for such modeling. Furthermore, the yields of array islands with their own redundant word and bit lines are combined using a new yield formula. Examples of the use of this technique for dynamic random-access memory (DRAM) chips are given. Finally, a simplified pragmatic approximation technique is discussed

Published in:

Defect and Fault Tolerance on VLSI Systems, 1991. Proceedings., 1991 International Workshop on

Date of Conference:

18-20 Nov 1991