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A data-reuse architecture for gray-scale morphologic operations

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6 Author(s)
Ming-hwa Sheu ; Nat. Cheng Kung Univ., Tainan, Taiwan ; Jhing-Fa Wang ; Chen, J.-S. ; An-Nan Suen
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Presents an efficient pipeline architecture to perform gray-scale morphologic operations. The features of the architecture are 1) lower hardware cost, 2) faster operation time in processing an image, 3) lower data access times from the image memory, 4) shorter latency, 5) suitability for VLSI implementation, and 6) adaptability for N×N morphologic operations

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Circuits and Systems II: Analog and Digital Signal Processing, IEEE Transactions on  (Volume:39 ,  Issue: 10 )