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Multiprocessor DSP architectures that implement the FCT based JPEG still picture image compression algorithm with arithmetic coding

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2 Author(s)
Ramaswamy, S.V. ; Northern Illinois Univ., De Kalb, IL, USA ; Miller, G.D.

Several parallel pipelined digital signal processor (DSP) architectures that implement the fast cosine transform (FCT)-based Joint Photographers Expert Group (JPEG) still picture image compression algorithm with arithmetic coding for entropy coding are described. The extended JPEG image compression algorithm's average execution time, when compressing and decompressing a 256×256 pixel monochrome still image, varied from 0.61 s to 0.12 s in architectures that contained from one to six processors. A common bus DSP multiprocessor system capable of meeting the critical timing requirements of digital image compression/decompression applications is also presented. In an effort to maximize DSP utilization, a simple static load distribution method is provided for assigning the load to the individual DSPs. These parallel pipelined DSP architectures can be used for a wide range of applications, including the MPEG implementation for video coding

Published in:

Consumer Electronics, IEEE Transactions on  (Volume:39 ,  Issue: 1 )

Date of Publication:

Feb 1993

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