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SAC: a systolic array controller chip

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3 Author(s)
R. Smith ; Dept. of Electr. Eng., Minnesota Univ., Minneapolis, MN, USA ; M. Dillon ; G. Sobelman

SAC (systolic array controller) is a chip designed for use with an NCR 16-bit fixed-point multiplier/accumulator (MAC) chip to form a two-chip cell in systolic arrays for signal processing applications. The SAC/MAC cell can be used as an inexpensive, flexible building block for either one-dimensional or two-dimensional systolic arrays in either application-specific or general-purpose machines. The SAC provides an interface to other cells via four parallel ports. It routes data to and from the companion high-speed MAC via one 16-bit bidirectional port, controls the MAC, and provides 64 words of scratchpad memory for programs and data

Published in:

Acoustics, Speech, and Signal Processing, 1988. ICASSP-88., 1988 International Conference on

Date of Conference:

11-14 Apr 1988