An expandable VLSI processor array approach to contour tracing

A new architecture for contour tracing of black-and-white images is described. This architecture uses parallelism and pipelining to achieve a significant increase in processing speed over previous tracers. An array of identical processors suitable for VLSI implementation is used. The array approach facilitates expansion to handle arbitrarily large images. The processors trace independently, thereby providing fully parallel, high-speed operation. A postprocessor links the partial contours created by the subdivision of the input image. Simulation results for compression ratio and number of operations are presented.<
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