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A single chip VLSI architecture for a real time stereo vision processor

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4 Author(s)

The architecture of a single-chip stereo vision processor is presented. It can carry out in real time a dynamic programming algorithm (or a Viterbi algorithm) to compute for each pixel the distance between two corresponding lines. An on-chip surviving-paths memorization and decoding is also described. A rough evaluation for a 1.2-μm CMOS process provides an area of less than 70 mm2

Published in:

Acoustics, Speech, and Signal Processing, 1988. ICASSP-88., 1988 International Conference on

Date of Conference:

11-14 Apr 1988