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A VHSIC demonstration radar signal processor

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2 Author(s)

An approach is being implemented that utilizes sophisticated computer-aided engineering (CAE) technology to facilitate meeting US Department of Defense advanced-technology-evaluation requirements for the Very High Speed Integrated Circuits (VHSIC) program. As a first step in this direction, a VHSIC Demonstration Radar Signal Processor (VDRSP) was designed, simulated, built, and tested. The VDRSP executes a standard moving-target-indication (MTI) function at a 5-MHz complex data rate. In order to minimize cost, schedule, and glue logic requirements, the VHSIC I IBM CMAC (Complex Multiply and Accumulate Chip) was selected for this project. The final system executes at a throughput of 450 million operations per second

Published in:

Aerospace and Electronics Conference, 1988. NAECON 1988., Proceedings of the IEEE 1988 National

Date of Conference:

23-27 May 1988