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The problem of mapping a general iterative algorithm with nonunit increment/decrement steps of the loop indices onto a systolic array using space-time transformation is studied. Necessary and sufficient conditions for the existence of such a space-time mapping are presented. The latency of a systolic computation is characterised in terms of the spa-time mapping and the increment/decrement step size of the iterative algorithm. Formulas for the latency of linear and 2D systolic arrays are derived. An efficient space-time mapping using restricted row operations which guarantees unit latency, thereby maximising the utilisation of the processors, is also proposed. Necessary and sufficient conditions under which column operations can be used to derive a legitimate space-time mapping are presented. A theory relating concurrent error detection and space-time mapping in systolic arrays is proposed. Based on this theory, existing (ad hoc) concurrent error detection approaches can be explained.
Computers and Digital Techniques, IEE Proceedings E (Volume:140 , Issue: 1 )
Date of Publication: Jan 1993