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Parallel DFT computation on bit-serial systolic processor arrays

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1 Author(s)
K. J. Jones ; Div. of Syst. Eng., Marconi Underwater Systems Ltd., Templecombe, UK

The paper shows how novel one-dimensional and two-dimensional systolic processing architectures, comprising up to N coordinate rotation digital computer (CORDIC) processing elements (PEs), can be used to carry out hardware-efficient parallel implementations of the N-point discrete Fourier transform (DFT), offering highly attractive throughput rates in relation to the conventional N-processor linear systolic array. The CORDIC PE is implemented in bit-serial form using single-bit half-adder (HA) and full-adder (FA) circuits. It is thus extremely efficient, in terms of speed/area product and possesses simple interconnects, facilitating the mapping of potentially thousands of such units onto a single chip.

Published in:

IEE Proceedings E - Computers and Digital Techniques  (Volume:140 ,  Issue: 1 )