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A vertically integrated GaAs bipolar/FET DRAM cell with internal gain

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3 Author(s)
Z. G. Ling ; Sch. of Electr. Eng., Purdue Univ., West Lafayette, IN, USA ; J. A. Cooper ; M. R. Melloch

The authors describe a novel dynamic memory cell incorporating a p-n junction storage capacitor, bipolar write-access transistor (BJT), and a junction field-effect transistor (JFET) for nondestructive readout with internal gain. The bipolar transistor is vertically integrated over the storage capacitor and the JFET is formed from the base region of the BJT. Internal gain improves the signal-to-noise ratio and eliminates the requirement that a specific number of electrons be stored in the cell for reliable readout.<>

Published in:

IEEE Electron Device Letters  (Volume:13 ,  Issue: 12 )