Trapping of net positive charge at low gate stress voltage, and of net negative charge at high gate stress voltage, is observed through changes in the gate-to-drain capacitance of the stressed junction. These observations can be explained in terms of electron trapping, hole trapping, and generation of acceptor-like interface states located in the upper half of the bandgap. Channel shortening is also observed and found to exhibit a logarithmic time dependence.<
Published in:
Electron Device Letters, IEEE
(Volume:13
,
Issue:
11
)
Date of Publication: Nov. 1992