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BiCMOS technology with 60 GHz n-p-n bipolar and 0.25 mu m CMOS

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8 Author(s)
Warnock, J. ; IBM Thomas J. Watson Res. Center, Yorktown heights, NY, USA ; Shahidi, G.G. ; Dasvari, B. ; Wu, B.
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A BiCMOS technology has been developed that integrates a high-performance self-aligned double-polysilicon bipolar device into an advanced 0.25 mu m CMOS process. The process sequence has been tailored to allow maximum flexibility in the bipolar device design without perturbation of the CMOS device parameters. Thus, n-p-n cutoff frequencies as high as 60 GHz were achieved while maintaining a CMOS ring oscillator delay per stage of about 54 ps at 2.5 V supply comparable to the performance in the CMOs-only technology. BiCMOS and BiNMOS circuits were also fabricated. BiNMOS circuits exhibited approximately=45% delay improvement compared to CMOS-only circuits under high load conditions at 2.5 V.<>

Published in:

Electron Device Letters, IEEE  (Volume:13 ,  Issue: 11 )