Referenced Items are not available for this document.
A general methodology for accurate estimation of defect-related yield loss in reconfigurable VLSI circuits is presented. Yield for replicated cells in the reconfigurable circuitry is estimated based upon a calculation of layout sensitivity to manufacturing defects of varying sizes. The important concept addressed is the need for separate estimation of reconfigurable and nonreconfigurable components of a replicated cell's critical area (CA) for accurate yield estimation. Two examples-a 256 kb SRAM and reconfigurable 32×32 port 32 b crossbar switch-are presented to illustrate the essential characteristics of the proposed yield estimation method
Published in:
Solid-State Circuits, IEEE Journal of
(Volume:28
,
Issue:
2
)
Date of Publication: Feb 1993
- Page(s):
- 146 - 156
- ISSN :
- 0018-9200
- INSPEC Accession Number:
- 4384028
- Digital Object Identifier :
- 10.1109/4.192046
- Product Type:
- Journals & Magazines
- Date of Current Version :
- 06 August 2002
- Issue Date :
- Feb 1993
- Sponsored by :
- IEEE Solid-State Circuits Society
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