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Accurate estimation of defect-related yield loss in reconfigurable VLSI circuits

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3 Author(s)
Khare, J. ; Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA ; Feltham, D.B.I. ; Maly, W.

A general methodology for accurate estimation of defect-related yield loss in reconfigurable VLSI circuits is presented. Yield for replicated cells in the reconfigurable circuitry is estimated based upon a calculation of layout sensitivity to manufacturing defects of varying sizes. The important concept addressed is the need for separate estimation of reconfigurable and nonreconfigurable components of a replicated cell's critical area (CA) for accurate yield estimation. Two examples-a 256 kb SRAM and reconfigurable 32×32 port 32 b crossbar switch-are presented to illustrate the essential characteristics of the proposed yield estimation method

Published in:

Solid-State Circuits, IEEE Journal of  (Volume:28 ,  Issue: 2 )

Date of Publication:

Feb 1993

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